This invention relates to superior silicon carbide integrated circuits and to methods for fabricating the same.
Silicon carbide is known to be a superior semiconductor material for high voltage and high frequency applications. The high voltage capability of SiC is due to its large critical electric field (2xc3x97106 V/cm), which is about 10 times higher than that of silicon. The SiC high voltage devices are expected to have 200 times smaller power loss when compared to a similarly rated Si device. SiC MOSFETs are expected to replace Si IGBTs and GTOs. However, the performance of low voltage, low power SiC devices is expected to be inferior to that of existing Si CMOS devices. The reason for this is: (1) the mobility of carriers in SiC is smaller than that in Si; and (2) the device technology of SiC is less mature than that of Si, which forces the feature size and power losses to be higher for low voltage SiC devices. There is increasing interest in providing a high voltage semiconductor device and a low voltage semiconductor device in a monolithic, same chip integrated circuit structure and particularly such a device on silicon carbide.
Additionally, silicon carbide is chemically inert in nature and is not attacked by most of the common etchants at room temperature due to the strong bond between carbon and silicon in monocrystalline silicon carbide. At the same time, the bonds between silicon and carbon in amorphous silicon carbide are weak. In my work with B. J. Baliga, it was reported that monocrystalline silicon carbide is not attacked by most of the common laboratory etchants, such as HF, HNO3, KOH, HCl, etc. while amorphous silicon carbide can be etched by treating it as a mixture of silicon and carbon. See Alok et al, Journal of Electronic Materials. Vol. 24, No. 4, pp. 311-314 and the similar disclosure of U.S. Pat. No. 5,436,174 wherein this fact is used to form trenches in a monocrystalline silicon substrate by directing first electrically inactive ions using ion-implantation into a first portion of the monocrystalline silicon carbide substrate to create an amorphous silicon carbide region followed by removal of the first amorphous silicon carbide region to form a trench in the monocrystalline silicon carbide using an etchant which selectively etches amorphous silicon carbide at a higher rate than monocrystalline silicon carbide.
U.S. Pat. Nos. 5,318,915, 5,322,802, 5,436,174, and 5,449,925 disclose procedures which use amorphization to create deep PN junctions or deep trenches in SiC wafers. However, these references do not produce integrated circuits that combine the advantages of silicon carbide and silicon, and do not provide for improvement in speed and performance of integrated circuits. Other workers in the art (JPA 55024482 and JPA 07082098) have attempted to create SiC areas in a Si wafer by converting a thin layer of Si into SiC using ion implantation. Such thin layers cannot be used to create high voltage ( greater than 1000V) power devices. Moreover, attempts in our laboratory to convert part of a Si wafer to SiC using high temperature ion implantation have been unsuccessful. There is a continued need in the art for integrated circuits that combine the excellent inversion layer mobility properties of silicon with the superior properties of silicon carbide for high voltage and high frequency applications and that comprise silicon low voltage devices and silicon carbide high voltage devices on a single chip.
An object of the invention is to provide novel silicon carbide devices in which low voltage semiconductor devices are fabricated in silicon regions on a silicon carbide substrate and in which high voltage lateral and/or vertical devices are fabricated in silicon carbide regions of the same silicon carbide substrate.
Another object of the invention is to provide such silicon carbide devices fabricated as a monolithic integrated circuit.
These and other objects of the invention will be apparent from the description of the invention that follows.
In my co-pending application Ser. No. 10/055,378 referred to above, a method is described and claimed for the production of silicon carbide devices which have an oxide region on
(a) either an amorphous silicon-rich region which is (i) predominantly or entirely amorphous silicon or (ii) a mixture of predominantly amorphous silicon in combination with amorphous silicon carbide and/or silicon dioxide or
(b) a monocrystalline silicon region;
wherein (a) or (b) is present on a region of a silicon carbide substrate, or
(c) a region of a silicon carbide substrate, and to novel silicon carbide devices derived therefrom.
In one specific embodiment, the method includes the steps of:
(a) amorphizing silicon carbide in at least one region of a monocrystalline silicon carbide substrate by ion implantation to break the Sixe2x80x94C bonds and convert the silicon carbide to amorphous silicon carbide;
(b) removing at least an effective amount of the carbon from the resulting amorphous silicon carbide with an etchant effective to selectively remove said effective amount of carbon from said amorphous silicon carbide to produce an amorphous silicon-rich region; and
(c) forming an oxide on said amorphous silicon-rich region, preferably by subjecting the etched region to thermal oxidation under conditions effective to preserve the amorphous silicon layer; or subjecting the etched region to thermal oxide under conditions that substantially remove the amorphous silicon layer; or subjecting the etched region to thermal oxidation to produce an oxide on an amorphous silicon layer and annealing to produce an oxide on monocrystalline silicon on a region of a silicon carbide substrate; or by first growing LTO on the etched region and then subjecting the LTO-bearing etched region to thermal oxidation and high temperature anneal to produce an LTO oxide on a monocrystalline silicon carbide substrate.
Thus, the inventive method reduces the interface states density and improves the inversion layer mobility by removing an effective amount of carbon from silicon carbide as described above and wherein the term xe2x80x9ceffective amountxe2x80x9d means that amount of carbon which when removed or that amount of silicon carbide which when amorphized and etched according to the invention is effective to reduce the interface states density between the silicon carbide region and the oxide region and thereby result in an improvement of the inversion layer mobility when compared to interface states density and inversion layer mobility of the unamorphized and/or unetched silicon carbide and/or that amount which when removed is effective to permit the formation of a substantially crystalline silicon region from an amorphous silicon carbide region.
In such method, the carbon need only be removed from the top surface as that is the only silicon carbide region which would be consumed during the oxidation process. However, the invention is not restricted to amorphization and removal of carbon from only the surface nor to treatment of any particular area of a substrate. Rather the invention contemplates a technique which selectively removes carbon from a selected region(s) of a silicon substrate, such as a silicon carbide wafer. Once the carbon is removed, thermal oxidation can be performed to provide a device having reduced interface states between the silicon carbide and thermal oxide. The method makes it possible to increase inversion layer mobility in SiC MOS devices. These MOSFET devices are useful as SiC high voltage ( greater than 1000V) ICs and may be used for a variety of commercial and military applications such as in locomotives, electric cars, combat vehicles, aircraft, lighting, etc.
This technology is also used in my present work, wherein it is desired to provide a superior class of high voltage integrated circuits (ICs) wherein silicon regions, preferably silicon islands, are formed in selective areas of SiC wafers. In such devices, it is possible to utilize SiC regions for the fabrication of devices requiring high voltage blocking capability, while using Si regions for fabrication of high speed logic and protection circuitry, i.e. low voltage power devices. It is desirable to have both Si and SiC regions on the same wafer for fabrication of high voltage devices accompanied with low voltage logic and control circuitry on the same chip. Fabrication of both high voltage and low voltage devices in the same semiconductor material leads to lower power loss and higher efficiency. It is therefore desirable to have both silicon and silicon carbide regions on the same wafer for fabrication of low and high voltage devices, respectively. This new class of integrated circuit yields lowest forward voltage drop when compared to Si or SiC power ICs.
The present invention provides at least one silicon region in a silicon carbide wafer in which may be fabricated a low voltage semiconductor device using techniques well known in the art, such as for example, MOSFET devices, BiCMOS devices, Bipolar devices, etc., and on the same chip, at least one silicon carbide region in which may be fabricated a high voltage (i.e.,  greater than 1000V) semiconductor device using techniques well known in the art, such as for example, LDMOSFET, UMOSFET, DMOSFET, IGBT, MESFET, and JFET devices.
Such devices may be fabricated using any of the procedures described in said Ser. No. 10/055,378 provided the steps are conducted to provide a substantially monocrystalline silicon region on a silicon wafer. Another method for forming said silicon regions is described hereinbelow with respect to FIG. 3.